1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device having an automatically adjusting function and a method of testing the same.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device having an automatically adjusting function. An automatically adjusting circuit 101 automatically adjusts a parameter with regard to an arbitrary target circuit 102. For example, the target circuit 102 is an output buffer of a data input/output circuit provided in DRAM. The automatically adjusting circuit 101 automatically adjusts an output impedance of the output buffer. This is disclosed in Japanese Laid Open Patent Application (JP-P2005-39549A). When the parameter is automatically adjusted, the target circuit 102 can operate in a corrected state.
In conjunction with the above description, a semiconductor integrated circuit device is disclosed in Japanese Laid Open Patent Application (JP-P2002-8393A). In this conventional example, the semiconductor integrated circuit device includes a memory circuit for performing a read operation in which a plurality of data are read out in parallel, a plurality of data lines to transfer the plurality of data outputted from the memory circuit, and a first signal transfer path to transfer a control signal for instructing the start of the read operation to the memory circuit. A first data latch circuit latches a signal level of an internal node in response to a test timing signal which is activated after a preset time elapse after the control signal is activated. The second signal transfer path transfers the test timing signal to the first data latch circuit. A data transfer path is arranged between one of the plurality of data lines and the internal node. A signal delay circuit is arranged in at least one of the first and second signal transfer paths.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2001-357671A). The semiconductor memory device of this conventional example has a memory cell array of memory cells which need a refreshing operation, and a write request and a write data are asynchronously supplied to an access address. An access section performs the refreshing operation on the memory cell array after performing a read or write for the access address to the memory cell array. A control section controls the access section to late write to the memory cell array by using a write data and the access address supplied in a memory cycle after a memory cycle in which the write request is supplied.